This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on patent application Ser. No(s). 092108023 filed in TAIWAN on Apr. 8, 2003, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The invention relates to a Phase Locked Loop (hereinafter called PLL), and more particularly to a phase frequency detector, which has high sensitivity and is applied to a PLL.
2. Description of the Related Art
The Phase Locked Loop (PLL) is an automatic control circuit capable of tracing the frequency and phase of an input signal. The PLL is widely used in computer and consumer products and used in the fields of frequency synthesis, clock/data recovery, clock de-skewing, and the like. The PLL traces the phase and frequency of the input signal and locks the phase and frequency of the output signal so as to keep the phase and frequency of the output signal at a desired value or within a certain range.
There are basically two types of PLLs, which are the analog PLL and the digital PLL. Both the analog PLL and the digital PLL need a phase frequency detector (hereinafter called PFD). FIG. 1A shows a block diagram of a typical digital PLL. The digital PLL includes a PFD 100, a PEQ (Phase Error Quantizer) 110, a DCO (Digital Controller Oscillator) 120 and a divider 130. The PFD 100 is for comparing a feedback signal Fi with an input signal Fr to get a phase error therebetween, and outputting phase error signals according to the phase error. The typical phase error signals includes an UP signal and a DOWN signal, and a phase error value between the feedback signal Fi and the input signal Fr is represented by the values of the two phase error signals and the time difference therebetween. The PEQ 110 quantizes the phase error value and outputs a count signal according to the values of the UP and DOWN signals and the time difference therebetween. The DCO 120 outputs a corresponding output signal Fo according to the value of the count signal. The feedback signal Fi is then obtained by dividing the output signal Fo in the divider 130.
FIG. 1B shows a block diagram of a typical analog PLL, which includes a PFD 150, a charge pump 160, a voltage controller oscillator (hereinafter called VCO) 170 and a divider 180. It is to be noted that the PFD 150 operates in the same way as the digital PLL, with the PEQ 110, the DCO 120, and the functions thereof being substituted by the charge pump 160 and the VCO 170.
FIG. 2 shows a circuit of a conventional PFD, which includes two D-type flip-flops 200 and 210 and an AND gate 220. The signal input terminals D of the flip-flops 200, 210 are coupled to a high-voltage power source. The flip-flop 200 receives the input signal Fr at a clock input terminal CK and generates the phase error signal UP at an output terminal Q. The flip-flop 210 receives the feedback signal Fi at a clock input terminal CK and generates the phase error signal DOWN at an output terminal Q. The AND gate 220 receives the two phase error signals UP and DOWN and generates a reset signal for the two flip-flops 200 and 210. Detailed description concerning the PFD in FIG. 2 can be referred to U.S. Pat. No. 5,963,058, which is incorporated herein by reference.
FIG. 3 is the timing chart showing the operation principle of the PFD. It is assumed that the flip-flops of the phase frequency detector in FIG. 2 are rising-edge triggered elements. Taking that the signal Fr leads the signal Fi as an example, the flip-flop 200 outputs the UP signal with high level when the input signal Fr is turned to high level from low level. The flip-flop 210 outputs the DOWN signal with high level when the input signal Fi is turned to high level from low level. When the UP and DOWN signals are both turned to high level, the AND gate 220 outputs a reset signal that is respectively inputted to the flip-flops 200 and 210 to reset the flip-flops 200 and 210. As a result, the UP and DOWN signals are returned to low level. The operation under the situation when the signal Fr lags behind the signal Fi can be similarly derived.
However, the gate delay inherent in circuit components of the PFD, such as the flip-flops and the AND gate, may significantly degrade the linear relationship between the length of the UP or DOWN signal, and the phase error of the Fr and Fi signals. This may also significantly limit the sensitivity, i.e., the minimum amount of the phase error between the feedback signal Fi and input signal Fr that can be detected by the PLL. When the phase error is smaller than a certain level, it is possible to induce a dead zone condition, in which the UP or DOWN signal outputted from the PFD cannot be utilized by the post-stage circuit, or even cannot be detected by the post-stage circuit owing to the above-mentioned delay nature of the circuit components.